1. Technical Field
This invention relates, generally, to a high performance serial cable bus, and, more specifically, to a high performance serial cable bus having topologies consisting of daisy chains or tree structures of cable hops, or a combination of both, but limited in an acyclic manner yet providing redundant path access to devices within the bus topology. More particularly still, the present invention relates to a high performance serial cable bus having automatic acyclic configuration devices in star configuration with dual controllers, and a means for switching devices from one controller domain to the other controller domain during a failure mode.
2. Description of the Related Art
Recently, the IEEE has established a High Performance Serial Bus according to Standard P1394 (hereafter referred to as P1394). The P1394 standard operates at speeds compatible with devices sending and receiving data at 100 megabits, 200 megabits, and 400 megabits per second, depending upon a particular device. Up to 63 devices are connectable as a single system on the P1394 bus. The P1394 requires that the bus structure follow a particular cable physical layer specification and cable bus topology and management services. Two types of topologies allowed under P1394 include the daisy chaining of cable hops or tree structures of cable hops, or a combination of both. FIG. 1 illustrates both a daisy chain topology and a tree topology, wherein the tree topology further illustrates subtopologies following the daisy chain topology. In the daisy chain topology nodes are connected on a peer to peer relationship, but only in an acyclic manner. Likewise, the tree topology is also acyclic, but provides for a client server or root and branch hierarchy.
The P1394 standard requires that the nodes have three stacked serial bus protocol layers: (1) the transaction layer, (2) the link layer, and (3) the physical layer. A P1394 link node has a unique physical ID (address), which is established during the initialization phases following a serial bus reset. The architecture layer that supports the initialization phases is the physical layer. In the cable topologies, this is referred to as the cable physical layer, to distinguish it from the backplane physical layer.
An example of a cable physical layer is illustrated in FIG. 2 and is hereinafter referred to as "PHY". PHY 25 must support the P1394 initialization phases, which include reset, tree-ID, and self-ID, in order for the bus to become initialized with each node having a unique physical ID, root assignment to one of the PHYs, and determining port connection status in a hierarchical structure pointing towards the root. The P1394 standard further defines a set of state machines that are implemented in PHYs to allow bus initialization to occur, but only if there are no loops in the cable topology. If there is a loop, a bus initialization timeout occurs, thus causing an error signal that can provide an error message warning of this event. The cable loop must then be "broken" and the serial bus must be reset again to start initialization.
Within PHY 25 are three PHY ports 22, 24, and 26. Each PHY port 22, 24, and 26 supports three external cable connector interfaces 28, 30, and 32, respectively, as well as an internal link to PHY interface 34. A PHY port 22, 24, and 26, also known as a serial cable interface, has low voltage differential drivers and receivers for two pair of signals TPA/TPA# and TPB/TPB#. These signals are propagated on pairs of twisted conductors in the cable that are used for DC signalling during bus initialization and arbitration phases, and for data/strobe encoded packet transmission and reception once the bus has been initialized. There is also a third twisted pair of conductors in the cable, which supplies unregulated PHY power and ground. This power pair allows PHY 25 to be powered from the cable, separate from the link power or unit power, so that the bus can be initialized even through a unit may be powered down.
An example of the two signal twisted pairs is illustrated in FIG. 3. Twisted pairs TPA (TPA/TPA#) and TPB (TPB/TPB#) are not only twisted in the cable (not shown), they are also crossed over in the cable so that TPA signals on one end of the cable become TPB signals on the other end, and vice versa. Also, the common mode voltage for the differential pair signalling is supplied from only one end of the cable for each cross over (TPA to TPB) twisted pair connection. Twisted pair bias (TpBias) is generated on each TPA connection and provides the common mode input voltage to the TPB circuit at the other end of the cable. This is important, because it allows each port to have a Port.sub.-- Status comparator on its TPB cable connectors to sense the presence of TpBias from the TPA connectors at the other end of the cable, thus determining whether or not a port connection exists.
Although FIG. 2 shows a three-port PHY, PHY implementations under P1394 may support many more ports, up to 27. This limitation is due to the self-ID packet format that P1394 defines. PHYs broadcast their self-ID packets during bus initialization to convey their physical ID, the number and state of the ports they support, and other configuration data.
The P1394 cable topologies form a repeater bus. After the initialization phases are complete, all PHYs have a physical ID, and a root node is established. A data packet transmitted from one node is propagated and repeated through all PHY ports (internal and external) throughout the bus. There is no packet routing based on node addresses; all nodes receive the data packet and it is up to their respective link layers to determine if the data packet is for that particular PHY or node, and whether it should acknowledge receipt of the data packet. Therefore, if a cable or PHY is or should become disconnected, it breaks the repeater path between nodes up stream and down stream from it. Consequently, there are PHY concentrators under P1394.
A PHY concentrator is a PHY having multiple ports, for example, at least 10. The number of ports supported is based on the physical constraints for packaging and other cost tradeoffs. The PHY concentrator allows for star or point-to-point connections for multiple nodes, and allows for removal of defective devices without breaking the packet repeater path or requiring recabling. PHY concentrators are particularly desirable in file server environments.
A block diagram of a PHY concentrator is depicted in FIG. 4. Initiator node 52 serves as a serial SCSI RAID adapter and is coupled to a PHY concentrator 50. PHY concentrator 50 is further connected to a plurality of discrete PHYs 54, each of which is further connected to a target node disk drive 56, which make up the RAID arrangement. (RAID stands for redundant array of inexpensive disks.) Any target node disk drive 56 can be disconnected without "breaking" the bus because of the point-to-point distribution allowed by the PHY concentrator 50. P1394 also supports hot plugging, so in a file server, especially with RAID support, the disk drives can be mounted in sliding drawers within an enclosure. Then, faulty disk drives can be removed and eventually replaced while the file system continues to run in a degraded mode.
In file server systems having high availability, it is desirable to maintain operation, albeit in a degraded mode, with any single point of failure. RAID systems have been developed as a solution to this problem. RAID-5 provides striping of data and parity across an array of disk drives so that when one drive fails, the data on the defective drive can be reconstructed with no loss of data. For higher availability, it is desirable to have the type of configuration shown in FIG. 5 in order to provide alternate paths to the disk drives and continued operation even when a controller fails. In FIG. 5, each hard disk drive is coupled to a first initiator node controller and a second initiator node controller, or PHY concentrator 50. Unfortunately, this arrangement would fail because each P1394 PHY must act as a repeater to all connected ports, and in this physical configuration, the interconnection between the PHY ports creates topology loops. In this arrangement, the bus would never pass the initialization phase.
Accordingly, what is needed is a way to provide redundant path access in an otherwise acyclic serial bus topology. Furthermore, the redundant path access must also be capable of allowing hot plug replacement of any component in the redundant path access.